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ISL5239
TABLE 15. MEMORY DATA LSW
TYPE: CAPTURE MEMORY, ADDRESS: 0x0c
BIT
15:0
BIT
15:0
BIT
15:14
13:12
10:0
BIT
15:14
FUNCTION
Memory Data <15:0>
FUNCTION
Memory Data <31:16>
FUNCTION
Reserved
Input Capture Status
Input Trigger Position
FUNCTION
Reserved
DESCRIPTION
Lower 16 bits of capture memory data word.
TABLE 16. MEMORY DATA MSW
TYPE: CAPTURE MEMORY, ADDRESS: 0x0d
DESCRIPTION
Higher 16 bits of capture memory data word. Writing to this address triggers the write to the memory and
increments the address counter when address auto increment, control word 0x04, bit 13 is set. Must write
control word 0x0c first, to load the data values into memory.
TABLE 17. INPUT MEMORY STATUS
TYPE: CAPTURE MEMORY, ADDRESS: 0x0e
DESCRIPTION
Not used.
Read only register with status defined as:
00 - Idle, Memory access OK.
01 - Armed. Capture memory waiting for trigger.
10 - Loading. Capture memory in load mode.
11 - Send. Memory sends data to downstream modules.
Read only register which records memory location of input trigger point. 2 0 to 2 11 (0...2047).
TABLE 18. FEEDBACK MEMORY STATUS
TYPE: CAPTURE MEMORY, ADDRESS: 0x0f
DESCRIPTION
Not used.
13:12
Feedback Capture Status Read only register with status defined as:
00 - Idle, Memory access OK.
01 - Armed. Capture memory waiting for trigger.
10 - Loading. Capture memory in load mode.
10
9:0
Reserved
Feedback Trigger
Not used.
Read only register which records memory location of feedback trigger point. 2 0 to 2 10 (0...1023).
Position
TABLE 19. CONTROL
TYPE: PRE-DISTORTER, ADDRESS: 0x10
BIT
15:3
2
1
0
FUNCTION
Reserved
Test
Bypass
Reset
24
DESCRIPTION
Not used.
Selects use of test inputs
0 - Off. IIN<17:0>, QIN<17:0> in use for input stream.
1 - On. Use capture memory output for pre-Distorter input. Note: Test inputs are 16-bits wide and are MSB
justified onto the pre-distorter 20-bit inputs by setting the four LSB’s to zero.
Disables processing and allows input data to flow to output without any pre-distorter modification.
0 - Pre-distorter is active and processing.
1 - Pre-distorter is bypassed.
Software generated logic reset, which when high, resets the pre-distorter circuitry. Low is default.
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